Presently, the embedded system, which was composed of SOC, entered into people's life more and more widely. We can see it frequently whether in the mobile phones, television, industrial control equipment or network devices. With the continuous expansion of network scale and the increase of service, the embedded Internet has played an increasingly important role. Ethernet is the most widely used LAN technology in the present day world. With the increasing use of embedded systems, the need for incorporating Ethernet connectivity into the embedded systems is greatly felt. Therefore, the study of Ethernet communication on embedded system is necessary. The embedded Ethernet is widely applied, and its research is very important.

LFSR‟s are the functional building blocks of circuits
like the pseudo-random noise (PN) code generator that are commonly used in Code Division Multiple Access (CDMA) systems. This application note describes two implementations of an SR4(Shift Register) primitive for area-efficient designs LFSR using the encryption and decryption algorithms using XOR gate in 180nm for less area and low power methodologies for ASIC designs using
Cadence design tools. The unusual sequence of values generated by an LFSR can be gainfully employed in the encryption and decryption of data. That makes the cryptography quite easy and useful for longer bit
lengths. A stream of data bits can be encrypted and decrypted by XOR-ing them with output from an identical LFSR‟s which finds the certain applications like Radio and visual broad casting schemes, Internet and Wireless communications. This work mainly concentrates on the 4 bit random number that uses for encryption that is mainly
works faster clock rates of 100MHz, which finds the application in wireless networks.

Any VLSI circuit is composed of the very basic unit that is the multiplier. As technology is increasing day by day many new designs are being evolved. As the design becomes bigger more will be the delay in it. If the delay in the basic unit that is multiplier can be decreased then the overall delay in the new designs can be effectively alleviated. There are many multipliers designed so far in the field of VLSI using different methods for its implementation. This paper presents implementation of a Modified Booth multiplier. So far many Modified Booth multipliers are implemented. In all the methods for generating the partial products „negi‟ the extra partial product bit is used due to which number of partial products generated will be N/2+1. If this „negi‟ bit in the partial products can be avoided and efficient way for generating 2‟s complement of negative partial product is used which generates conversion signals, and then the number of partial products will decrease to N/2. For addition of partial products the design uses the 4:2 compressors to reduce the complexity in the circuit involved.

In these paper implementing fault detection and repair of word redundancy MBISR (Memory Built In Self Repair) using March SS and march RAW algorithms. A new micro coded BIST architecture is presented here which is capable of employing new test algorithms like March SS and March RAW that have been developed for coverage of some recently developed static and dynamic fault models. The same hardware has been used to implement other new March algorithms. This requires just changing the Instruction storage unit, or the instruction codes and sequence inside the instruction storage unit. The instruction storage unit is used to store predetermined test pattern. The simulation results have shown that the micro-coded MBIST architecture described here is an effective testing method to test embedded memories as it provides a flexible approach and better fault coverage. Just as March SS, any other new march algorithm can also be implemented using the same BIST hardware by changing the instructions in the microcode storage unit, without the need to redesign the entire circuitry. The word redundancy uses spare words in place of spare rows and columns. This repair mechanism avoids lengthy redundancy calculations as suggested by some other authors in their works as it stores faulty location addresses immediately supporting on-the-fly fault repair. Moreover, it can be interfaced easily with existing MBIST logic.